CH7009 TV Encoder / DVI Transmitter Combo Device - Chrontel - The world's leading supplier of PC-TV encoders

Device Status : ACTIVE
Features Description Datasheets Application Notes Technical Bulletins

Features

DVI Transmitter up to 165M pixels/second
DVI low jitter PLL
DVI hot plug detection
TV output supporting graphics resolutions up to 1024x768 pixels
Macrovision™ 7.1.L1 copy protection support
Programmable digital interface supports RGB and YCrCb
True scale rendering engine supports underscan in all TV output resolutions
Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering
Support for all NTSC and PAL formats
Provides CVBS, S-Video and SCART (RGB) outputs
TV connection detect
Programmable power management
10-bit video DAC outputs
Fully programmable through serial port
Complete Windows and DOS driver support
Low voltage interface support to graphics device
Offered in a 64-pin LQFP package

Note :
Our CH7010B is the Non-Macrovision™ version.

Description

The CH7009 is a display controller device which accepts a digital graphics input signal, and encodes and transmits data through a DVI (DFP can also be supported) or TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide variable voltage data port which supports five different data formats including RGB and YCrCb.

The DVI processor includes a low jitter PLL for generation of the high frequency serialized clock, and all circuitry required to encode, serialize and transmit data. The CH7009 comes in versions able to drive a DVI display at a pixel rate of up to 165MHz, supporting UXGA resolution displays. No scaling of input data is performed on the data output to the DVI device.

The TV-Out processor performs non-interlace to interlace conversion with scaling and flicker filters, and encodes the data into any of the NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to enable superior text display. Eight graphics resolutions are supported up to 1024 by 768 with full vertical and horizontal underscan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. Support is provided for Macrovision™ and RGB bypass mode which enables driving a VGA CRT with the input data.

ORDERING INFORMATION

Part Number Package Type RoHS Compliant # of Pins Voltage Supply

CH7009B-TF Lead Free - LQFP Yes 64 3.3V

CH7009B-TF-TR Lead Free - LQFP in Tape and Reel Yes 64 3.3V

| Sales Inquiry : Sales@chrontel.comm | Product Information: Info@chrontel.com

< Product End-Of-Life announcement > The CH7009A family which includes CH7009A-T, CH7009A-TF, CH7010A-T, CH7010A-TF, CH7011A-T, CH7011A-TF, CH7012A-T, CH7012A-TF, CH7301A-T and CH7301A-TF products is no longer available or supported by Chrontel effective March 5, 2008.

CH7009A-T and CH7009A-TF are obsolete device. Not recommended for new designs, please send email to Info for more information. The replacement is CH7009B-TF.

* Terms and Conditions of Sales

	Datasheets
	Click here to open the CH7009B Full Data Sheet.

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	Application Notes
	Crystal Oscillator, AN-06.pdf .
	PCB Layout and Design Considerations for CH7009A DVI/TV Output Device, AN-34.pdf .
	CRT Discharge Protection, AN-38.pdf .
	CH7009A Registers Read/Write Operation, AN-41.pdf .
	Recommendation of Composite & S-Video in single connector for CH7009A, AN-46.pdf .
	Composite & S-Video in Single Connector for CH7009A Using DACs Switching Method, AN-48.pdf .
	Optimizing Operating Temperature for CH7009A DVI/TV Output Device, AN-53.pdf .
	A PCB Design Guideline to Prevent DVI Signaling Power-Reverting in CH7009A, AN-57.pdf .
	CH7009A SDTV/HDTV Encoder TV Connection Detection, AN-60.pdf .
	DACs Connection Detection of CH7009 Encoders, AN-71.pdf .

	Technical Bulletins
	PC Motherboard with CH7009A Design Consideration, TB-26.pdf .
	Input/Output Timing Diagram of CH7009A TV Encoders, TB-29.pdf .
	Explanation for the Flickering Display Using Multi-sync TV in PAL Modes, TB-34.pdf .
	A Guideline to measure Crystal and Color-Burst Frequencies, TB-37.pdf .
	New Method to Improve CH7009A REv. C/D PLL Stability, TB-38.pdf .
	DVI Output Eye Diagrams of CH7009A vs. CH7009B, TB-41.pdf .
	PCB Design Considerations of DAC outputs with Multiple Video Formats, TB-45.pdf .
	Limitation of SDTV Encoder Scaling Engine, TB-47.pdf .

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