Device Status : ACTIVE
 
 
Features
  • Input data path handles 8, 12, or 16-bit words in multiplexed or non-multiplexed form
  • Decodes pixel data in YCrCb (CCIR601 or 656) or RGB (15, 16 or 24-bit) formats
  • Supports 640x480, 640x400, 720x400, 800x600 and 512x384 input resolutions
  • Adjustable underscan for most modes
  • High quality 4-line flicker filtering
  • High resolution on-chip PLL
  • Fully programmable through serial port
  • Supports NTSC, NTSC-EIA (Japan), and PAL (B, D, G, H, I, M and N) TV formats
  • Provides Composite, S-Video and SCART outputs
  • CCIR624-3 compliant (see exceptions)
  • Auto-detection of TV presence
  • Sub-carrier genlock and dot crawl control
  • Programmable power management
  • 9-bit video DAC outputs
  • Complete Windows and DOS driver software
  • Offered in 44-pin PLCC, 44-pin TQFP (1.4 mm)

Description

Chrontel's CH7005 digital PC to TV encoder is a stand-alone integrated circuit which provides a PC 99 compliant solution for TV output. Suggested application use with the Intel i740.* It provides a universal digital input port to accept a pixel data stream from a compatible VGA controller (or equivalent) and converts this directly into NTSC or PAL TV format.

This circuit integrates a digital NTSC/PAL encoder with 9-bit DAC interface, and new adaptive flicker filter, and high accuracy low-jitter phase locked loop to create outstanding quality video. Through its true scale scaling and deflickering engine, the CH7005 supports full vertical and horizontal underscan capability and operates in 5 different resolutions including 640x480 and 800x600.

A new universal digital interface along with full programmability make the CH7005 ideal for system-level PC solutions. All features are software programmable through a standard serial port, to enable a complete PC solution using a TV as the primary display.

* Terms and Conditions of Sales

Datasheets
Click here to open the CH7005 Full Data Sheet (397 KB, 4/25/01)
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Application Notes
Crystal Oscillator, AN-06.pdf (50 KB, 7/26/01)
PCB Layout considerations for CH7005, AN-24.pdf (16 KB)
Recommendation of Composite & S-Video in single connector for CH7005, AN-27.pdf (20 KB, 4/25/01)
CRT discharge protection, AN-38.pdf
CH7005 Registers Read/Write Operation, AN-47.pdf (73 KB, 4/25/01)
Composite & S-Video in Single Connector for CH7005 Using DACs Switching Method, AN-49.pdf (23 KB, 4/3/01)
Technical Bulletins
Crystal specifications for Macrovision Approval, TB-12.pdf (9 KB)
A list of different for the CH7004, CH7005 and CH7007, TB-18.pdf (15 KB)
Digital PC to TV Encoder with Macrovision, TB-19.pdf (16 KB)
Serial port tranreceiver with CH7005 under multiple display environment, TB-20.pdf (12 KB)
Serial port operation for CH7005, TB-22.pdf (41 KB)
CH700x Reconstruction filter, TB-24.pdf (16 KB)
A guideline to minimize noise in TV Encoder Caused by noisy DC power source, TB-28.pdf (18 KB)
Input/Output Timing Diagram of CH7005 TV Encoders, TB-29.pdf (27 KB)
A Guideline to Reliably Minimize Noise Embedding in PLL Power Source, TB-30.pdf (15 KB)
Explanation for the Flickering Display Using Multi-sync TV in PAL Modes, TB-34.pdf (17 KB, 5/8/01)
A Special Treatment for H Sync in Sync-Master Mode, TB-35.pdf (33 KB, 5/30/01)
A Guideline to Measure Crystal and Color-Burst Frequencies, TB-37.pdf (20 KB, 9/17/01)
Limitation of SDTV Encoder Scaling Engine, TB-47.pdf (7/2/04)

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