Features

TV-Out:

• VGA to TV conversion supporting up to 1024x768 pixels.
• Macrovision™ 7.1.L1 copy protection support (CH7017 only, CH7018 is non- Macrovision™ version).
• Two variable-voltage digital input ports.
• Simultaneous LVDS and TV output.
• True scale rendering engine supporting under-scan in all TV output resolutions. †¥
• Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering. ¥
• Support for NTSC and PAL TV formats.
• Outputs CVBS, S-Video, RGB and YPrPb.
• Support for SCART output.
• TV / Monitor connection detect.
• Output video switch for easy wiring to connectors.

• Single / Dual LVDS transmitter.
• Dual LVDS supporting pixel rates up to 330Mpixels/sec when both 12-bit input ports are ganged together.
• Panel fitting scaler – up scale to 1600x1200 pixels.
• LVDS low jitter PLL accepting EMI reduction input.
• LVDS 18-bit and 24-bit outputs.
• 2D dither engine.
• Panel protection and Power-Down sequencing.
• Programmable power management.

• Support for second CRT DAC bypass mode
• Four 10-bit video DAC outputs
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Variable voltage interface to graphics device
• Offered in a 128-pin LQFP package

¥† Patented Technologies

Description

The CH7017/CH7018 is a Display Controller device that accepts two digital graphics input data streams. One data stream outputs through an LVDS transmitter to a LCD panel, while the other data stream is encoded for NTSC or PAL TV and outputs through four 10-bit high-speed DACs. The TV encoder device encodes a graphics signal up to 1024x768 resolution and outputs the video signals according to NTSC or PAL standards. The LVDS transmitter operates at pixel speeds up to 165MHz per link, supporting 1600x1200 panels at 60Hz refresh rate.

The device can also accept one graphics data stream over two 12-bit wide variable voltage ports which support nine different data formats including RGB and YCrCb (RGB must be used for LVDS output). A maximum of 330M pixels per second can be output through dual LVDS links.

The TV-Out processor will perform non-interlaced to interlaced conversion with scaling, flicker filtering, and encoding into any of the NTSC or PAL video standards. The scaler and flicker filter are adaptive and programmable for superior text display. Eight graphics resolutions are supported up to 1024 by 768 pixels with full vertical and horizontal under-scan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. Anti-copy protection support is provided by Macrovision™ technology (CH7017 only). In addition to TV encoder modes, bypass modes are included which allow the TV DACs to be used as a second CRT DAC.

The LVDS transmitter includes a panel fitting up-scaler and a programmable dither function for the support of 18-bit panels. Data is encoded into commonly used formats, including those detailed in the OpenLDI and the SPWG specifications. Serialized data outputs on three to eight differential channels.

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