Device Status : ACTIVE
 

Features

TV-Out:

  • VGA to TV conversion supporting up to 1024x768 pixels
  • Macrovision™ 7.1.L1 copy protection support
  • Two variable-voltage digital input ports
  • Simultaneous LVDS and TV output
  • True scale rendering engine supporting under-scan in all TV output resolutions †¥
  • Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering ¥
  • Support for NTSC and PAL TV formats
  • Outputs CVBS, S-Video, RGB and YprPb
  • Support for SCART connector
  • TV / Monitor connection detect
LVDS-Out:
  • Single / Dual LVDS transmitter
  • Dual LVDS supporting pixel rate up to 330Mpixels/sec. 
    when both 12-bit input ports are ganged together
  • LVDS low jitter PLL accepts spread spectrum input
  • LVDS 18-bit and 24-bit outputs
  • 2D dither engine
  • Panel protection and power down sequencing
  • Programmable power management
  • Support for second CRT DAC bypass mode
  • Four 10-bit video DAC outputs
  • Fully programmable through serial port
  • Complete Windows and DOS driver support
  • Variable voltage interface to graphics device
  • Offered in a 128-pin LQFP package

¥† Patented Technologies

Description

The CH7019 is a Display Controller device which accepts two digital graphics input data streams. One data stream outputs through an LVDS transmitter to an LCD panel, while the other data stream is encoded for NTSC or PAL TV and outputs through a 10-bit high speed DAC. The TV encoder device encodes a graphics signal up to 1024x768 resolution and outputs the video signals according to NTSC or PAL standards. The LVDS transmitter operates at pixel speeds up to 165MHz per link, supporting 1600x1200 panels at 60Hz refresh rate. 

The device can also accept one graphics data stream over two 12-bit wide variable voltage ports which support nine different data formats including RGB and YCrCb (RGB must be used for LVDS output). A maximum of 330M pixels per second can be output through dual LVDS links.

The TV-Out processor will perform non-interlaced to interlaced conversion with scaling, flicker filtering, and encoding into any of the NTSC or PAL video standards. The scaler and flicker filter are adaptive and programmable for superior text display. Eight graphics resolutions are supported up to 1024 by 768 with full vertical and horizontal under-scan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. Support is provided for Macrovision™. In addition to TV encoder modes, bypass modes are included which allow the TV DACs to be used as a second CRT DAC.

The LVDS transmitter includes a programmable dither function for support of 18-bit panels. Data is encoded into commonly used formats, including those detailed in the OpenLDI and the SPWG specifications. Serialized data outputs on three to six differential channels.

 

ORDERING INFORMATION
Part Number Package Type RoHS Compliant # of Pins Voltage Supply
CH7019B-TF Lead Free - LQFP Yes 128 3.3V
CH7019B-TF-TR Lead Free - LQFP
in Tape and Reel
Yes 128 3.3V

| Sales Inquiry : Sales@chrontel.comm  |  Product Information: Info@chrontel.com

 

* Terms and Conditions of Sales

Datasheets
CH7019 Datasheet
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  Application Notes
Crystal Oscillator, AN-06.pdf (50 KB, 7/26/01)
CRT discharge protection, AN-38.pdf (8/30/02)
PCB Layout and Design Considerations for CH7019 LVDS/TV Output Device, AN-51.pdf (8/28/03)
Guideline to the Operation of EMI Emission Reduction of CH7019, AN-59.pdf (7/15/02)
CH7019 SDTV/HDTV Encoder TV Connection Detection, AN-60.pdf (9/25/02)
CH7019 Registers Read/Write Operation, AN-61.pdf (10/18/02)
DACs Connection Detection of CH7019 Encoders, AN-71.pdf (7/30/03)
PCB Layout and Design Considerations for CH7019B LVDS/TV Output Device, AN-72.pdf (7/2/04)
  Technical Bulletins
Input/Output Timing Diagram of CH7019 TV Encoders, TB-29.pdf (27 KB)
Explanation for the Flickering Display Using Multi-sync TV in PAL Modes, TB-34.pdf (17 KB, 5/8/01)
A Guideline to Measure Crystal and Color-Burst Frequencies, TB-37.pdf (20 KB, 9/17/01)
Low color-burst explanation, TB-39.pdf (9/25/02)
Explanation of CH7019 LVDS Power Sequencing, TB-40.pdf (10/22/03)
LVDS Dithering, TB-44.pdf (8/13/03)
PCB Design Considerations of DAC outputs with Multiple Video Formats, TB-45.pdf (9/9/03)
Limitation of SDTV Encoder Scaling Engine, TB-47.pdf (7/2/04)

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