Device Status : ACTIVE
 
Features
  • YPrPb support for 480i, 576i, 480p and 576p Output
  • Macrovision™  7.1.L1 copy protection support
  • Programmable digital input interface supporting RGB and
    YCrCb input data formats
  • Interlaced to progressive scan conversion for DVD
  • Support for NTSC, PAL TV and Progressive Scan formats
  • Support for SCART output
  • TV connection detection
  • Outputs of CVBS, S-Video and YPrPb
  • Two sets of individual DAC output pins, CVBS, S-Video and YPbPr to allow
    switching among TV- out connectors without additional external video switches
  • Programmable power management
  • Four 10-bit video DAC outputs
  • Fully programmable through serial port
  • Offered in a 48-pin LQFP package

Description

The CH7205 is a video TV encoder device for DVD application which accepts a digital video input signal, encodes and transmits data through four 10-bit high speed DACs. The device is able to generate synchronization signals for NTSC and PAL TV standards with CVBS, S-Video outputs, and YPrPb interface 480i, 576i, 480p and 576p consumer video outputs.

The device accepts data over one 12-bit (or 8-bit) wide data port with dual edge clock data transfer for multiplexed data (24 bit or 16 bit) through variable voltage data port which supports 5 different data formats including RGB and YCrCb.

A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. Support is provided for Macrovision ™ . ITU-R BT.656 interlaced video can be input and scan converted to non-interlaced video.

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Datasheets
CH7205 Full Data Sheet
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  Application Notes
Crystal Oscillator, AN-06.pdf (50 KB, 7/26/01)
CRT discharge protection, AN-38.pdf (8/30/02)
PCB Layout and Design Considerations for the CH7205 DVD/TV Encoder, AN-55.pdf
CH7205 SDTV/HDTV Encoder TV Connection Detection, AN-60.pdf
CH7205 Registers Read/Write Operation, AN-61.pdf
DACs Connection Detection of CH7205 Encoders, AN-71.pdf
  Technical Bulletins
Input/Output Timing Diagram of CH7205 TV Encoders, TB-29.pdf (27 KB)
Explanation for the Flickering Display Using Multi-sync TV in PAL Modes, TB-34.pdf (17 KB, 5/8/01)
PCB Design Considerations of DAC outputs with Multiple Video Formats, TB-45.pdf (9/9/03)
Limitation of SDTV Encoder Scaling Engine, TB-47.pdf (7/2/04)
Explanation of Edge Distorted Display on Low-end TVs, TB-48.pdf (7/12/04)

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