• Support DisplayPort Specification version 1.1a.
• Support 1 Main Link Lane at either 1.62Gb/s or 2.7Gb/s link rate for notebook PC applications
• Support input color depth 6, 8-bit per pixel for RGB format
• Support Enhanced Framing mode
• Support VESA and CEA timing standards up to 1440x900 resolution in 8-bit input and 1680x1050 resolution in 6-bit input with 60Hz refresh rate
• Support dynamic refresh rate switching
• Support seamless transition between progressive and interlaced input timing
• Support gamma correction and dithering
• Fast and full Link Training for embedded DisplayPort system
• Flexible TCON output control, 8 programmable GPOs for driving Source or Gate drivers in TFT- LCD panel
• Programmable LCD panel power sequence
• 6-bit single bus RSDS output interface
• Support RSDS output pin swapping for top or bottom mount PCBs
• Support internal test pattern
• Blank panel during invalid input
• Backlight luminance level control through AUX channel
• Support loading of a serial EEPROM when power up
• Programmable power management
• Support EMI reduction features including data de-scrambling, spread spectrum input clock and RSDS output.
• Achieve bit error rate <10-9 for raw transport data per lane and symbol error rate <10-12 for control data.
• Low power consumption, 180mW
• Offered in a 64-pin QFN package

Description

Chrontel’s CH7507 is a DisplayPort receiver that combines a timing controller (TCON) with Reduced Swing Differential Signaling (RSDS) output driver interface for the notebook display. This device receives high-speed serialized video data and uses its highly functional, fully programmable TCON to provide support for LCD panel modules. The integrated RSDS interface, operating in low-voltage and low EMI emission, is capable to drive WSXGA (1680x1050) resolution display panel for an embedded DisplayPort system.

The CH7507 is designed to comply with DisplayPort Specification 1.1a. Its receiver block supports a single Main Link lane with data rate running at either 1.62Gb/s or 2.7Gb/s. The device can accept input data in 18-bit 6:6:6 or 24-bit 8:8:8 RGB digital format. To further optimize the display quality and power dissipation, this device is equipped with seamless display refresh rate switching and progressive to interlace timing dynamic change capabilities.

The high performance CH7507 TCON consists of programmable logic blocks for processing video data and generating timing control signals to interface with Gate drivers and Source drivers in the TFT-LCD. During system power-up, setting the power on/off sequence for a particular panel can be achieved through CH7507’s TCON configuration registers. This timing control information is stored in the EEPROM along with the EDID information that will be used during the Link training through AUX Channel.

The CH7507 has incorporated a luminance control function to interface with LCD backlight module. Brightness control commands sent through AUX Channel are dynamically translated by CH7507 and converted into LCD backlight control signals. In addition, each time if panel’s luminance level has been changed, the CH7507 will update the EEPROM with the new setting. Therefore the last brightness adjustment value will already be restored when next time system is powered up or returns from its standby mode.

The advanced Power Management Unit (PMU) is designed to reduce power consumption in normal operation.