CH7012B

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Features


  • TV output supporting up to 1024x768 graphics resolutions

  • Programmable digital interface supports RGB and YCrCb

  • True scale rendering engine supports underscan in all TV output resolutions

  • Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering

  • Support for all NTSC and PAL formats

  • Provides CVBS, S-Video and SCART (RGB) outputs

  • TV connection detect

  • Programmable power management

  • 10-bit video DAC outputs

  • Fully programmable through serial port

  • Complete Windows and DOS driver support

  • Low voltage interface support to graphics device

  • Offered in a 64-pin LQFP package






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Note:
CH7012 is the Non Macrovision™ version.

Describe

The CH7012B is a Display controller device which accepts a digital graphics input signal, and encodes and transmits data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide variable voltage data port which supports five different data formats including RGB and YCrCb.

The TV-Out processor will perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data into any of the NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to enable superior text display. Eight graphics resolutions are supported up to 1024 by 768 with full vertical and horizontal underscan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. Support is provided for Macrovision™ and RGB bypass mode which enables driving a VGA CRT with the input data.

Structure diagram

Data sheet

 Click here to open the CH7012 Full Data Sheet.

Application Desc


  •   Crystal Oscillator, AN-06.pdf (50 KB, 7/26/01)

  •   CRT discharge protection, AN-38.pdf

  •   CH7010A Registers Read/Write Operation, AN-41.pdf.

  •   PCB Layout and Design Considerations for CH7012 TV Output Device, AN-45.pdf (736 KB)

  •   Composite & S-Video in Single Connector for CH7010A Using DACs Switching Method, AN-48.pdf.

  •   CH7010A SDTV/HDTV Encoder TV Connection Detection, AN-60.pdf.

  •   DACs Connection Detection of CH7010 Encoders, AN-71.pdf.

Technical Report


  •   Input/Output Timing Diagram of CH7010 TV Encoders, TB-29.pdf (27 KB)

  •   Explanation for the Flickering Display Using Multi-sync TV in PAL Modes, TB-34.pdf (17 KB, 5/8/01)

  •   A Guideline to Measure Crystal and Color-Burst Frequencies, TB-37.pdf (20 KB, 9/17/01)

  •   New Method to Improve CH7010A REv. C/D PLL Stability, TB-38.pdf.

  •   Low color-burst explanation, TB-39.pdf (9/25/02)

  •   PCB Design Considerations of DAC outputs with Multiple Video Formats, TB-45.pdf.

  •   Limitation of SDTV Encoder Scaling Engine, TB-47.pdf (7/2/04)

Specifications

Input Interface  DVO , TTL/Digital RGB, TTL/YCbCr

Output Interface  CVBS , S-Video, SCART

Audio Interface   No

Other features  Scaler, Line Buffer

Package Type  LQFP64

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